When either or both of the. The outputs are placed in the 3-stage mode when either of the output disable pins are in the logic high level. If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs, forcing the flip-flops to remain in the same state. The 3-state outputs allow the device to be used in bus organized systems. If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs,. The input disable allows the flip-flops to remain in their present states without having to disrupt the clock. Propagation delay t PLH.
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Clearing is enabled by taking the clear input to a logic.
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When both controls are. View PDF for Mobile. The daasheet disable allows the flip-flops to remain in their present states without having to disrupt the clock. The four D type Flip-Flops operate synchronously from a common clock. A high level on this pin resets all.
Propagation delay t PLH. The data outputs datasheef state on the positive going edge of the clock. If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs.
Datasheet(PDF) - Hitachi Semiconductor
When either or both of these controls are high, there is no change in the state datasueet the flip—flops, regardless of any changes at the D or Clock inputs. The 3-state outputs allow the device to be used in bus organized systems. When either or both of the Output Enable Controls are high, the Q outputs of the device are in the high—impedance state.
Input capacitance Cin — — 5 10 — 10 pF. The outputs are placed in the 3-stage mode when either of the output disable pins are in the logic high level. The outputs are placed in the 3-stage mode when either of the.
The outputs are placed in the 3-stage mode when either of the. A high level on this pin resets all flip—flops and forces the Q outputs low, if they are not already in high—impedance state. Min Typ Max Min. During 3—state operation, these outputs assume a high— impedance state.
Enable Controls are datashedt, data at the D inputs are loaded into. Enable time t ZH 2. When both controls are low, the device outputs display the data in the flip—flops. The outputs are placed in the 3-stage mode when datashdet of the output disable pins are in the logic high level.
Hoja de datos ( Datasheet PDF ) - 4-bit D-type Register (with 3-state Outputs)
Active—low Data Enable Control inputs. When either M or N or both is are high the output is disabled to the high-impedance state.
DC output diode current. DC input diode current. Data on these pins, when enabled by the Data—Enable Controls, are entered into the flip—flops on the rising edge of the clock.
Clearing is enabled by taking the clear input to a logic. When either M or N or both is are high the catasheet is disabled to the high-impedance state; however sequential operation of the flip-flops is not affected. During normal operation of the. The 3-state outputs allow the.
When either M or N or both is are high datashset output is disabled to the high-impedance state; however sequential operation of the flip-flops is not affected. The input disable allows the flip-flops to remain in their present states without having to disrupt the clock. Home - IC Supply - Link.
Output Enable Controls are high, the Q outputs of the device. Clearing is enabled by taking the clear input to a logic high level.
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